1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a poly-silicon gate with reduced numbers of photolithography processes. Consequently, the problem of gate bridging is improved.
2. Description of the Related Art
Referring to FIG. 1A to FIG. 1D, a cross sectional view of the process of a conventional MOS transistor device is shown. Firstly, as shown in FIG. 1A, a semiconductor substrate 10 having an N-well and a P-well formed therein is provided. A field oxide layer 12 is formed on the semiconductor substrate 10 to isolate the active region. The field oxide layer 12 is formed by local oxidation of silicon (LOCOS), or shallow trench isolation (STI).
The gate 14 is formed as shown in FIG. 1B. Using thermal oxidation, a gate oxide layer 13 is formed. A poly-silicon layer 14 doped with an impurity to enhance the conductivity is deposited. Using first photolithography and etching process, the poly-silicon layer 14 is defined, and the gate 14 is formed.
Referring to FIG. 1D, a second photolithography process is performed. A photo-resist layer 17 is formed to cover the N-well. Using the gate 14 as the mask, implant N-type impurity into the P-well to form source/drain region 18. The photo-resist layer is then removed. The conventional MOS transistor device is formed.
It is shown in the above conventional process for the MOS transistor device that, the formation of source/drain region needs three steps of photolithography process. Whereas the photolithography for the formation of lightly doped drain (LDD) has not been counted. Since the misalignment is inevitable to happen during exposure for photolithography process, the more numbers of photolithography processes are performed, the less the reliable the device is. Though it is not shown in the figure, a gate bridging is very likely to happen in a conventional method due to the misalignment during exposure. Thus, a better process is in need.